The Up/Down control input line simply enables either the upper string or lower string of AND
gates to pass the Q/Q’ outputs to the succeeding stages of flip-flops. If the Up/Down control
line is “high,” the top AND gates become enabled. If the Up/Down control line is made “low,”
the bottom AND gates become enabled. Design a UP/Down counter circuit in VHDL to count
the number of bits in a register. The up and down counter Flow chart is shown in Figure 1.
The answer produced by the algorithm is stored in the Register.
Figure 1. UP/DOWN Counter Flow chart Diagram
(b) Draw an ASM chart that represents the algorithm.
(c) Design the Datapath circuit.
(d) Design the hardwired control unit using one flip-flop per state technique
(e) Write the VHDL code for your design.
(f) Simulate and verify the functionality of your design by using Altera’s quartus II software.
(You may download and install the software directly from Altera’s web site,
https:/www.altera.com/support/software/download/altera_design/quartus_we/dnlquartus_we.jsp) MUST BE DESIGNED USING THIS SOFTWARE ONLY. Please provide the