(b) Consider the system in question 1. The sampling rate is again chosen to be 10 kHz….

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(b) Consider the system in question 1. The sampling rate is again chosen to be 10 kHz. It is required to design an appropriate compensator such thatthe resulting closed-loop system has an overshoot less than 25% and a settlingtime less than 8 milliseconds as well as a steadystate errorto be less 1% due to a step reference of 1 micrometer. i) Can you design a digital lead compensatorthat would achieve the above design specifications? ii) If your answer is yes, please give your solutions togetherwith all detailed derivations and simulation results. If youransweris no, then, give your reasons together with detailed justification. Use MATLAB and SIMULINK wherever necessary.

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