You must design and simulate the combinational logic required for a BCD to 7-Segment Decoder with the following items: I. Compile a truth table for the BCD to 7-segment decoder 2. Derive minimised logic equations showing the dependence of the decoder outputs ‘a tog’, on BCD inputs ‘A to B’. in NAND only form. The method for minimisation must be the Karnaugh map. 3. Illustrate your circuit designs using a schematic diagram created in ISIS. 4. Simulate your circuit designs from ISIS using Proteus V&A, to confirm correct operation. 5. Produce appropriate PCB layout for the design using Proteus. 6. Document your results in a report and submit your report.